This invention relates to the field of power supply regulation and control. In particular, some embodiments of this invention are directed to power supply regulation for optimal performance and efficiency trade-off for digital logic supplies.
In digital circuits, the maximum operating clock speed is typically limited by the maximum path delay of the combinational logic, the RC delay time of the routing, the setup and hold times of the flip-flops, and the clock skew of the clock supplied to the flip-flops. However, the gate delays can vary for a given design due to process variations or operating conditions. Therefore, devices fabricated based on a given design can have great variations in their performance. Digital designers spend ample time trying to ‘close timing’ after a design has been synthesized and routed. They use RC extraction models and Process, Voltage and Temperature (PVT) corners to analyze the timing, such that under the worst case PVT corner, the flip-flops are guaranteed to latch the expected data. It can be seen that a great deal of effort is spent in circuit design to resolve issues caused by variations in device performance. Therefore, an improved way to manage variations in device performance is highly desirable.